The benchmark library
A guide to your next experiment.
Understand the abstraction levels, gate libraries, clocking schemes, and file formats behind MNT Bench.
Explore benchmarksFrom logic to layout
The library at a glance
Open an illustration to see the full-size reference.
Two technologies
Gate libraries
Benchmarks are provided for two different gate libraries.
Controlling the flow
Clocking schemes
Up to five different clocking schemes are available.
Working with your download
File formats & naming
Downloads are ZIP archives containing network-level Verilog
.v files and gate-level fiction .fgl files.
The filenames describe the configuration of each layout.
Not every benchmark is necessarily available for every possible configuration of the available options. For example, for large circuits, layouts using the USE clocking scheme have not been found yet.
| Level | Filename | Example |
|---|---|---|
| Gate-level | <benchmark_identifier>_<library>_<clocking_scheme>_<algorithm>_<optimized>_<input-ordered>_<cost_objective>.fgl |
|
| Best gate-level layout | <benchmark_identifier>_<library>_BEST.fgl |
mux21_ONE_BEST.fgl |
| Network level | <benchmark_identifier>.v |
mux21.v |
The work behind the library
Research references
Explore the original benchmark collections, design methods, and optimizations.
Benchmark collections
Physical design
Optimization
Tools
Verification & further reading
Related research
Additional FCN design methods. Inclusion here does not imply that layouts generated with these methods are available in MNT Bench.
- One-Pass Synthesis for Field-coupled Nanocomputing Technologies · ASP-DAC 2021
- Efficient Multi-Path Signal Routing for Field-coupled Nanotechnologies · NANOARCH 2022
- Ending the Tyranny of the Clock: SAT-based Clock Number Assignment for Field-coupled Nanotechnologies · IEEE NANO 2024
- Reducing Wire Crossings in Field-Coupled Nanotechnologies · IEEE NANO 2024
- Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions · IEEE NANO 2024
- A Fully Planar Approach to Field-coupled Nanocomputing: Scalable Placement and Routing Without Wire Crossings · IEEE NANO 2025
- Minimizing Area and Delay in Planar Physical Design for Field-coupled Nanocomputing · IEEE NANO 2026
- Toward Compact Planar Circuits for Atomic-Scale Computing: A Hybrid Crossing Elimination Flow · IEEE NANO 2026