Physical Design
Physical design transforms a logical circuit representation into a tangible, manufacturable layout. This process sits at the intersection of geometry, timing, power, thermal management, and lithography, imposing stringent constraints and requiring delicate trade-offs. As technology nodes continue to scale into the sub-nanometer regime and heterogeneous integration becomes a mainstay, physical design faces unprecedented complexities—billions of interconnected devices, multiple power domains, intricate design rules, and performance-critical data paths.
By orchestrating the placement of standard cells, the routing of interconnects, and the integration of macros and input/output pins, physical design ensures the final chip layout meets its functionality, performance, and manufacturability objectives. Simultaneously, it must handle a cascade of competing goals: minimum area, low power consumption, high throughput, thermal stability, and strict compliance with Design for Manufacturability (DFM) and Design for Reliability (DFR) rules. As an essential part of the Electronic Design Automation (EDA) flow, physical design resonates with the themes of logic synthesis, technology mapping, and sign-off verification, forming an integrated pipeline that ultimately yields high-quality silicon implementations.
Despite the availability of robust commercial tools, the complexity and variability in modern System-on-Chip (SoC) designs still push physical design to its limits. Open research challenges include achieving timing closure at extremely high clock frequencies, balancing multi-objective optimizations (area, power, timing, and noise), and accommodating advanced packaging technologies like chiplets or 2.5D/3D integration. Moreover, as new computing paradigms and device technologies emerge, physical design must adapt to place and route heterogeneous components with vastly different geometries, materials, and physical properties.
Our Work
Our group’s research in physical design aims to advance the state-of-the-art algorithms, methodologies, and frameworks for producing high-quality chip layouts under complex constraints. By focusing on scalability, adaptability, and robustness, we seek to push the boundaries of what is possible, reducing turnaround time and elevating the quality of results for designs of ever-increasing complexity. Our main research activities include:
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Cell Placement and Congestion Management: At the granular level, our placement techniques adaptively position millions of standard cells to minimize wirelength, reduce routing congestion, and balance timing and power distribution. We utilize advanced data structures, partitioning methods, and machine learning heuristics to efficiently navigate the immense search space, ensuring that placement solutions are both scalable and high-quality.
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Global and Detailed Routing: We focus on routing algorithms that achieve top-tier performance by navigating dense routing resources while respecting complex design rules and ensuring signal integrity. Our research includes global routing solutions that approximate optimal topologies quickly, and detailed routers that carefully assign wires to tracks to ensure DRC-clean layouts.
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Benchmarking and Tool Development: We provide robust evaluation frameworks to measure and compare the performance of physical design algorithms. Our benchmarking methodologies, standardized data sets, and open-source utilities enable fair comparisons and meaningful progress tracking, fostering a collaborative research environment that encourages reproducibility and transparency.
Furthermore, we apply our physical design expertise to emerging domains like nanotechnology and microfluidic devices.
Contact
In case you have any further questions, please do not hesitate to contact us via physical-design.cda@xcit.tum.de.