Mapping to Superconducting Architectures
Superconducting quantum processors have limited qubit connectivity and restricted two-qubit interactions. Quantum circuits must therefore be mapped carefully to satisfy these constraints, as mapping choices directly affect circuit depth, error accumulation, and execution fidelity. Efficient, automated mapping methods are essential to minimize additional routing and basis-adjustment operations while producing high-fidelity implementations.
We developed three configurable approaches:
- General mapping for arbitrary circuits: applicable to any architecture with restricted connectivity. Experimental evaluations demonstrate consistent improvements over baseline heuristics. Details are summarized in “An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures”
- Specialized mapping for SU(4) benchmark circuits: tailored to structured circuits used to evaluate compiler performance and optimization techniques. Details are summarized in “Compiling SU(4) Quantum Circuits to IBM QX Architectures”
- Optimal/minimal-overhead mapping: formulates the task as a symbolic optimization problem, producing mappings with the minimal number of routing and basis-adjustment operations for small circuits. Details are summarized in “Mapping Quantum Circuits to IBM QX Architectures Using the Minimal Number of SWAP and H Operations”
These methods are available as part of the open-source MQT quantum circuit mapping tool (MQT QMAP) .
Compilation for Superconducting Bus‑Resonator Architectures
In contrast to general superconducting architectures, bus-resonator architectures provide effective all-to-all interactions among qubits coupled to a shared resonator. This advantage, however, comes at the cost of substantial overhead from single-qubit MOVE operations. Realizing the full potential of such hardware thus requires sophisticated compilation techniques that minimize this overhead.
In “Quantum Circuit Compilation for Superconducting Bus-Resonator Architectures” , we present the first formalization of the underlying compilation problem for bus-resonator architectures amenable to so-called SAT-CP solvers. This formalization yields optimal solutions for small quantum circuits. For larger instances, we propose a linear-time heuristic. Experimental evaluations confirm that the formalization makes it possible to find optimal solutions even in vast search spaces and that the heuristic provides near-optimal compilation while scaling efficiently to circuits of practical size. Together, these contributions establish both a rigorous baseline and a practical path toward low-overhead compilation for superconducting bus-resonator devices.
MQT Bench Online Tool
To evaluate the correspondingly developed methods, we provide the benchmark suite MQT Bench, a cross-level benchmark library designed to accelerate innovation across quantum software, hardware, and AI. For more details, please refer to the Section on MQT Bench
Contact
In case you have any problems with or questions, feel free to contact us via quantum.cda@xcit.tum.de .
