Welcome to the Munich Nanotech Benchmark Library (MNT Bench)!

The development and improvement of physical design tools for nanotechnologies, such as Silicon Dangling Bonds (SiDBS), is critical to the success of this emerging technology. Furthermore, simulation and fabrication heavily rely on the usage of area-efficient layouts. To compare the results of new physical design algorithms and provide the most optimal layouts found thus far, this benchmark suite offers common benchmark functions in the field combined with the best state-of-the-art layouts w.r.t. to area. In addition to layouts using different gate sets, such as the QCA ONE📄 gate library for Quantum-dot Cellular Automata (QCA) or Bestagon📄 for Silicon Dangling Bonds (SiDBS), the following benchmark library also differentiates between different underlying clocking schemes such as 2DDWave📄, USE📄, RES📄, ESR📄 , or ROW📄. Furthermore, all layouts have been verified using fiction's equivalence checker📄.

All layouts can be downloaded as fiction gate-level layouts files (.fgl), which can be parsed and generated by fiction.

The respective publications for the gate libraries, benchmarks, clocking schemes, physical design algorithms, and optimization algorithms can be found by clicking the corresponding paper (📄) symbol.

In order to create a benchmark set according to your needs, simply fill out the form below.

Benchmark Selection

Please select the desired benchmarks from the set of all available ones or select all .

Trindade16📄 Benchmarks :
Multiplexer 2:1
XOR 2:1
XNOR 2:1
Half Adder
Full Adder
Parity Generator
Parity Check
Fontes18📄 Benchmarks :
t
t_5
b1_r2
majority
majority_5_r1
newtag
clpl
1bitAdderAOIG
1bitAdderMaj
2bitAdderMaj
XOR5Maj
xor5_r1
cm82a_5
parity
ISCAS85📄 Benchmarks :
c17
c432
c499
c880
c1355
c1908
c2670
c3540
c5315
c6288
c7552
EPFL📄 Benchmarks :
ctrl
router
int2float
cavlc
priority
dec
i2c
adder
bar
max
sin

Technology Selection

Next, technological specifications for the selected benchmarks must be chosen. The gate library defines the selection of gates that can be used, while the clocking scheme defines the underlying arrangement of clock zones on the layout. For details, see the level description.

Abstraction Level

Select the abstraction level:

Gate Library

Select the used gate library:

Clocking Scheme

Select the underlying clocking scheme:

Choose Best to automatically select the best clocking scheme, physical design algorithm and optimizations w.r.t. layout area:

Physical Design Algorithm

Select the physical design algorithm used to create the chosen layouts:

Optimization Algorithm

If Ortho or NanoPlaceR has been chosen, please also select the applied optimization algorithms:

If gold has been chosen, please also select the cost objective: ❓

Download

Number of selected benchmarks:  
0
     
File Size (compressed):  
0
     
File Size (uncompressed):  
0
 
After the download button is clicked, all benchmark functions provided as .v files and selected layouts provided as .fgl files are downloaded as a .zip archive. Details of the file format are provided. Alternatively, a pre-generated archive with all benchmarks can be downloaded.
Overview of Selected Benchmarks:

Reference

For a more detailed description of MNT Bench, we are referring to the corresponding paper "MNT Bench: Benchmarking Software and Layout Libraries for Field-coupled Nanocomputing". Our implementation is available on GitHub. In case you are using MNT Bench in your work, we would be thankful if you referred to it by citing the following publication:

@inproceedings{hofmann2024mntbench,
  author={Hofmann, Simon and Walter, Marcel and Wille, Robert},
  booktitle = {{2024 Design, Automation and Test in Europe (DATE)}},
  title={{{MNT Bench}}: Benchmarking Software and Layout Libraries for Field-coupled Nanocomputing},
  year={2024},
}

If you use any of the algorithms in your work, please consider citing them as shown on this page.

In case you have any problems or questions feel free to contact us via nanotech.cda@xcit.tum.de. More on our work on nanotechnologies is summarized on this page.